Field of the Invention
The invention relates to a capacitor array structure and more particularly relates to a capacitor array structure capable of reducing a parasitic capacitance with respect to a substrate or a metal wire.
Description of Related Art
In today's semiconductor industry, capacitors are very important and basic components. Among them, the metal-oxide-metal (MOM) capacitor structure is a common capacitor structure, the basic design of which is to fill an insulating medium between the positive metal plate and the negative metal plate that serve as the two electrodes, such that the positive metal plate and the negative metal plate and the insulating medium therein can form a capacitor unit. According to the design of the capacitor structure, generally, the unit capacitance is enhanced by reducing the thickness of the insulating medium between the electrodes or increasing the electrode surface area.
Besides, when the capacitor structure with parasitic capacitance is implemented in a circuit, the parasitic capacitance generated by the metal plates will also affect the overall performance of the circuit. Therefore, how to reduce the parasitic capacitance that may cause interference is also an important factor in the design of the capacitor structure. As the demand for semiconductor miniaturization continues to grow, how to improve the capacitor structure under the existing manufacturing specification to reduce interference of the parasitic capacitance has become an important research topic. In particular, for a circuit architecture composed of a large number of capacitors, the parasitic capacitance has a direct impact on the overall performance of the circuit. For example, the architecture of SAR (Successive Approximation Register) ADC (Analog-to-Digital Converter) requires a capacitor array of a large number of capacitors, and for most capacitors in the capacitor array, one of the electrodes is connected with one another. Referring to FIG. 1, FIG. 1 is a simplified circuit diagram of the capacitor array for SAR ADC. The capacitor array circuit 10 includes a plurality of capacitors C1, C2, C3, . . . , and CN, and one of the ends of each of the capacitors C1, C2, C3, . . . , and CN has a common potential. In other words, if the capacitors C1, C2, C3, . . . , and CN have the MOM capacitor structure, one of the metal electrodes of each of the capacitors C1, C2, C3, . . . , and CN may be connected with one another and have a common potential. Thus, if the metal electrode of the common potential generates a parasitic capacitance with the other objects around (e.g., substrate or metal wire), the overall circuit performance of the SAR ADC will be affected significantly.